Semiconductor devices are typically manufactured using one of two different types of semiconductor substrate: bulk substrate and silicon-on-insulator or semiconductor-on-insulator (SOI) substrate. Bulk fabricated devices employ a monolithic semiconductor substrate with no buried layers. SOI substrates have a buried layer of an insulating material, typically silicon dioxide (SiO2), under the electronic devices.
It is well known in the art that SOI and bulk fabricated devices have different benefits and different applications. For example, SOI devices can have the advantages of reduced parasitic capacitance and lower power consumption compared to bulk fabricated devices. In comparison, bulk fabricated devices can provide other advantages such as control of body voltage, which can be used to adjust the threshold voltage of an FET device. Also, bulk fabricated devices can typically have a lower manufacturing cost and higher power-handling capability. Therefore, the choice between SOI and bulk fabrication typically depends upon circuit application and performance requirements.
Integrated circuits using both SOI and bulk devices on a single wafer would provide the most useful solution for circuit designers because the advantages of both kinds of devices could be exploited. However, conventional wafer processing techniques make this task very difficult to accomplish. One significant problem with integrating SOI and bulk devices on a single substrate is making electrical connections between the devices. In the past, electrical connections between SOI and bulk device regions have been made in the wiring layers. Unfortunately, wiring layers for connecting the SOI and bulk devices increase the size of the circuit. This is particularly an issue for high-density memory circuits and microprocessors.
It would be an advance in the art to provide a simple, inexpensive method for fabricating both bulk and SOI devices on a single substrate. It would be particularly useful to provide small size electrical connections between the SOI and bulk devices on a single substrate.
It is also well known that crystal orientation can greatly affect the switching speed and current-carrying capability of field effect transistors and other semiconductor devices. For example, P-type complementary metal-oxide semiconductor (CMOS) transistors can have 2-3 times higher charge carrier mobility in {110}-oriented silicon compared to {100}-oriented silicon. Similarly, N-type CMOS devices can have about 2 times higher charge carrier mobility in {100}-oriented silicon compared to {110}-oriented silicon. A wafer with only {110} or only {100} crystal orientation therefore cannot provide both P-type and N-type devices with maximum carrier mobility. For maximum carrier mobility in both P-type and N-type devices, a wafer with both {110} and {100} regions is necessary.
Several methods are known for making hybrid substrates with both {110} and {100} regions. However, in prior hybrid wafer fabrication techniques it can be difficult to provide electrical connections across the {110} and {100} regions. In the past, electrical connections have been made using wiring layers, which is undesirable.
Therefore, it would be an advance in the art to provide a simple and inexpensive method for making devices having different crystal orientations on a single hybrid substrate. It would be particularly useful to provide small size connections between the regions of different crystal orientations.